Various types of circuits and devices are vulnerable to damage from electrostatic discharge (ESD). ESD occurs when a user of the circuit or device becomes electrostatically charged, for example by friction or induction, and then discharges through a pin or contact pad of the circuit or device. Integrated circuits (ICs), particularly ICs containing MOS (metal-oxide semiconductor) transistors, are vulnerable to such ESD damage. ESD may be inadvertently applied to input/output (I/O) or power pins or other pads of the IC, which can damage sensitive semiconductor junctions, dielectrics, interconnections, or other sub-elements of the IC.
Various protection techniques have been developed to protect circuitry from ESD. The main goal of ESD protection is to shunt ESD current away from vulnerable circuitry and through a special circuit path designed to dissipate such events. Thus, the high voltage and current caused by an ESD event is diverted away from the main circuitry of the IC. Such ESD circuits or structures (sometimes referred to as ESD protection circuits or clamps) may, for example, be placed in parallel across two input pins or pads, such as an I/O pad and ground, and therefore also in parallel across sensitive circuitry coupled to the two pads. Desirably, such ESD protection is unobtrusive or “invisible” to the normal operation of the circuit, so that its presence does not slow or otherwise negatively impact the operation of the remaining IC circuitry when no ESD event is occurring.
A common technique to prevent ICs from being damaged by ESD events uses a “multi-finger” ESD protection transistor device on the input/output pads of ICs. A multi-finger ESD protection transistor device is a series of transistors placed in parallel like “fingers” across the input/output pads of an IC so that it can have relatively large device widths to discharge ESD currents to ground potential. To function properly, the activation or “trigger” voltage of the multi-finger ESD protection transistor device should be larger than the operating voltage of the other devices not used for ESD protection. As such, the multi-finger ESD protection transistor device should not activate during normal operation of the circuit.
A well-known problem with multi-finger ESD protection transistor devices is the possibility of non-uniform triggering of the finger transistors. That is, in some instances, only the first finger transistor of the multi-finger device may activate, causing the current passing therethrough to exceed the design limitations. To ensure uniform activation of all of the finger transistors of the multi-finger ESD protection transistor device, one known approach is to add ballasting resistors in the substrate adjacent to each finger transistor to increase the resistance of the substrate and thereby the trigger voltage of the subsequently triggered finger transistor (on the basis of Ohm's law, voltage increases in proportion to resistance). For instance, the substrate resistance can be increased by increasing the distance of the substrate contact from the source/drain region of the transistor, or by increasing the P-well or N-well sheet resistance.
In some prior art examples, for sufficient ESD robustness of the ESD devices in CMOS integrated circuits, a salicide (self-aligned silicide) blocking (SAB) layer can be disposed on the substrate to block salicide formation over any ballasting resistors, which protects these resistors from silicidation during source/drain contact formation, thereby allowing these resistors to maintain an appropriate ballast resistance to increase the current uniformity, as noted above. In advanced processes for forming high-k gate dielectric and metal gates, however, a SAB layer may not be desirable due to the increase in surface area required for such a structure. That is, advanced processes commonly employ smaller device pitches, which do not permit the surface area or spacing required between each finger transistor when a SAB layer is employed. Hence, a design that sustains high ESD robustness in fully-salicided ESD devices (i.e., those devices not employing an SAB layer) is desirable.
Accordingly, it is desirable to provide integrated circuits with an improved ESD protection functionality to maximize uniform triggering of the finger transistors. It is further desirable to provide fully-silicided, multi-finger ESD protection transistor devices that minimize the footprint or area required for their operation. Still further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.